ECE361: Digital Systems and Computer Design

Executive Summary

ECE 361 is an undergraduate-level course on computer organization and processor design. This course explores the fundamental organization and design of computer systems, starting from computer architecture and instruction set architecture (ISA), through processor datapath and control design, to arithmetic logic units (ALUs), memory organization, and input/output (I/O) systems. The course also introduces SystemVerilog for modeling, implementing, and testing processor components and computer systems, providing students with hands-on experience in hardware-oriented system design. Pre: 205 and 260, or consent.

Logistics

  • CRN

    ECE361 001ECE361L 001ECE361L 002ECE361L 003
    77422776437764477645

  • Personnel

    Role / PersonnelAssigned SessionOffice Hours / Notes
    Lecturer: Yao ZhengN/Asee here
    TA: Chohao YuSession 1 (T 09:00am - 11:45am)TBD
    TA: Chohao YuSession 2 (T 13:30pm - 16:15pm)TBD

  • Classroom

    TimeLocationTextbook/HWHW/Exam Effort
    MWF 09:30am-10:20amHolmes Hall 242Logic Design and Verification Using SystemVerilog (Revised) by Donald ThomasIndividual
    Computer Organization and Design: The Hardware/Software Interface — MIPS Edition by Patterson and Hennessy

  • Laboratory

    SessionTimeLocationReport Effort
    01T 09:00am - 11:45amHolmes Hall 451Group
    02T 13:30pm - 16:15pmHolmes Hall 451Group

Grading

  • Breakdown1
Midterm Exam 1Midterm Exam 2Final ExamHomeworks / Take-Home Quizzes
25%25%25%25%
  • Cutoffs
AA-B+BB-C+CC-D+DD-F
90%87%83%80%77%73%70%67%63%60%57%<57%
  • Proscribed Conduct: Copying or otherwise cheating on homework, lab reports, or exam will result in a failing grade for the course. More details can be found at student conduct code policies, III.C.

Schedule

Lecture

Lecture

TIMETOPICSREADING / HW / EXAMDEADLINE
Week 1 — Mon. 8/24/2026Introduction / Review Part 1: DataData representation, conversions, signed integers, arithmetic–
Week 1 — Wed. 8/26/2026Review Part 2: Logic OperationsLogic operations and Boolean concepts–
Week 1 — Fri. 8/28/2026Review Part 3: Combinational CircuitsCombinational logic and circuit design–
Week 2 — Mon. 8/31/2026Review Part 4: Sequential CircuitsSequential logic and state–
Week 2 — Wed. 9/2/2026SystemVerilog I: Combinational CircuitsSystemVerilog modeling of combinational circuits–
Week 2 — Fri. 9/4/2026SystemVerilog I: SimulationSimulation and verification basics–
Week 3 — Mon. 9/7/2026NO INSTRUCTION — Labor Day––
Week 3 — Wed. 9/9/2026SystemVerilog I: Sequential CircuitsSequential circuit modeling–
Week 3 — Fri. 9/11/2026SystemVerilog I: Additional ConstructsAdditional SystemVerilog concepts–
Week 4 — Mon. 9/14/2026Computer Architecture Overview I: Introduction and PerformancePatterson & Hennessy, Sec. 1.1–1.6–
Week 4 — Wed. 9/16/2026Computer Architecture Overview II: DesignPatterson & Hennessy, Sec. 1.7–1.11–
Week 4 — Fri. 9/18/2026ISA I: Barely CProgramming model and preparation for MIPS ISA–
Week 5 — Mon. 9/21/2026ISA II: CPU and Instruction ExecutionMIPS ISA–
Week 5 — Wed. 9/23/2026ISA IIIMIPS instructions and data operations–
Week 5 — Fri. 9/25/2026ISA IV: Instruction FormatsMIPS instruction encoding and formats–
Week 6 — Mon. 9/28/2026ISA V: StackStack organization and usage–
Week 6 — Wed. 9/30/2026ISA Practice / Quiz / Problem SolvingReview and practice–
Week 6 — Fri. 10/2/2026ISA VI: SubroutinesProcedure calls and subroutines–
Week 7 — Mon. 10/5/2026ISA VII: System-Level ConceptsSystem-level ISA concepts–
Week 7 — Wed. 10/7/2026ISA Review / Problem SolvingReview and practice–
Week 7 — Fri. 10/9/2026Processor I: Single-Cycle ProcessorSingle-cycle datapath and control–
Week 8 — Mon. 10/12/2026Processor II: PipelinePipelining fundamentals–
Week 8 — Wed. 10/14/2026Processor II: Pipeline, continuedPipeline stages and timing–
Week 8 — Fri. 10/16/2026Processor III: Pipeline ImplementationPipelined datapath implementation–
Week 9 — Mon. 10/19/2026Processor IV: HazardsPipeline hazards–
Week 9 — Wed. 10/21/2026Processor V: Data HazardsMidterm Exam 1 — Take Home opens12:01 AM
Week 9 — Fri. 10/23/2026Processor VI: Control HazardsBranches and control hazards–
Week 10 — Mon. 10/26/2026Processor VII: Dynamic PredictionMidterm Exam 1 — Take Home due11:59 PM
Week 10 — Wed. 10/28/2026Memory I: BasicsMemory hierarchy fundamentals–
Week 10 — Fri. 10/30/2026Memory II: Blocks and CachesCache blocks and mapping–
Week 11 — Mon. 11/2/2026Cache and Memory ReviewMemory hierarchy review and practice–
Week 11 — Wed. 11/4/2026Memory III: TechnologiesMemory technologies–
Week 11 — Fri. 11/6/2026ALU I: Integer ArithmeticInteger arithmetic–
Week 12 — Mon. 11/9/2026ALU II: Integer MultiplicationMultiplication hardware and algorithms–
Week 12 — Wed. 11/11/2026NO INSTRUCTION — Veterans Day––
Week 12 — Fri. 11/13/2026ALU III: Floating PointFloating-point representation and arithmetic–
Week 13 — Mon. 11/16/2026ALU ReviewALU review and practice–
Week 13 — Wed. 11/18/2026Processor ReviewProcessor, pipeline, memory, and ALU review–
Week 13 — Fri. 11/20/2026Processor / Memory ReviewReview and problem solving–
Week 14 — Mon. 11/23/2026SystemVerilog II: Hardware Threads and Clock DomainsMidterm Exam 2 — Take Home opens12:01 AM
Week 14 — Wed. 11/25/2026SystemVerilog II: Hardware Thread Interaction and InterfacesThread interaction and interfaces–
Week 14 — Fri. 11/27/2026NO INSTRUCTION — Thanksgiving Period––
Week 14 — Sun. 11/29/2026–Midterm Exam 2 — Take Home due11:59 PM
Week 15 — Mon. 11/30/2026SystemVerilog III: Testbenches and RandomizationVerification testbenches and constrained randomization–
Week 15 — Wed. 12/2/2026SystemVerilog III: Assertions and SequencesAssertions, properties, and sequences–
Week 15 — Fri. 12/4/2026I/O: IntroductionI/O fundamentals and system integration–
Week 16 — Mon. 12/7/2026I/O: Applications and ExamplesI/O applications and design examples–
Week 16 — Wed. 12/9/2026Final ReviewComprehensive final review–
Study Period — 12/11/2026–12/12/2026Study Period––
Finals — Mon. 12/14/2026Final Exam — In PersonComprehensive Final Exam9:45–11:45 AM

Note: Lecture topics are organized from the provided ECE361 slide set. Midterm placement follows the natural gaps and review material in that sequence; adjust the two midterm dates if the official Fall 2026 exam plan differs.

Laboratory

Lab Schedule

TIMELABTOPICDEADLINE
Week 1–2 — 8/25–9/8/20261Unix/Linux9/8, 11:59 PM
Week 3–4 — 9/8–9/22/20262C Language9/22, 11:59 PM
Week 5–6 — 9/22–10/6/20263SystemVerilog I10/6, 11:59 PM
Week 7–8 — 10/6–10/20/20264QtSPIM and MIPS10/20, 11:59 PM
Week 9–10 — 10/20–11/3/20265FPGA11/3, 11:59 PM
Week 11–12 — 11/3–11/17/20266CPU Research11/17, 11:59 PM
Week 13–15 — 11/17–12/8/20267Pipeline Processor12/8, 11:59 PM

  1. The grading breakdown is subject to change at the discretion of the instructor and in accordance with the University grading system and policies. ↩︎