ECE260: Introduction to Digital Design
Executive Summary
This course explores the foundation of digital circuit design, starting from Boolean algebra, through combinational and sequential logic, to finite state machines and basic central processing units (CPUs) under von Neumann architecture. The associated laboratory segment introduces modern digital design techniques, e.g., Verilog hardware description language (HDL) and field-programmable gate array (FPGA), to model, implement, and test the aforementioned digital circuits. Pre: 160 or 110 or ICS 111 or consent.
Logistics
CRN
ECE260 001 ECE260 002 ECE260 003 78638 78639 78640 Personnel
Role / Personnel Assigned Session Office Hours / Notes Lecturer: Yao Zheng N/A see here TA: Anindya Bal Session 1 (R 09:00am - 11:45am) TBD TA: Anindya Bal Session 2 (R 13:30pm - 16:15pm) TBD TA: Ziyu Chen Session 3 (R 16:30pm - 19:15pm) TBD Classroom
Time Location Textbook/HW HW/Exam Effort MWF 11:30 am-12:20pm Kuykendall Hall 101 EE260: Introduction to Digital Design Individual Laboratory
Session Time Location Report Effort 01 R 09:00am - 11:45am Holmes Hall 451 Group 02 R 13:30pm - 16:15pm Holmes Hall 451 Group 03 R 16:30pm - 19:15pm Holmes Hall 451 Group
Grading
Breakdown1
Participation Challenge Labs Midterms (2) Final 5% 15% 25% 30% 25% Cutoffs
A- B- C- 85% 75% 60% Proscribed Conduct: Copying or otherwise cheating on homework, lab reports, or exam will result in a failing grade for the course. More details can be found at student conduct code policies, III.C.
Schedule
Lecture
| TIME | TOPICS | READING/HW/EXAM | DEADLINE |
|---|---|---|---|
| Week 1 (8/24, 8/26, 8/28) | Course Logistics and Introduction | Read/HW 01 | 8/30, 11:59PM |
| Week 2 (8/31, 9/2, 9/4) | Combinational Logic: Number Systems | Read/HW 02 | 9/6, 11:59PM |
| Week 3 (9/7) | NO INSTRUCTION — Labor Day | – | – |
| Week 3 (9/9, 9/11) | Combinational Logic: Switches, Transistors, Logic Gates | Read/HW 03 | 9/13, 11:59PM |
| Week 4 (9/14, 9/16, 9/18) | Combinational Logic: Boolean Algebra | Read/HW 04 | 9/20, 11:59PM |
| Week 5 (9/21, 9/23, 9/25) | Combinational Logic: More Gates and Combinational Logic Devices | Read/HW 05 | 9/27, 11:59PM |
| Week 6 (9/28) | Combinational Logic: Design Process | – | – |
| Week 6 (9/30) | Midterm I Review | – | – |
| Week 6 (10/2) | Midterm I — In Person | – | – |
| Week 7 (10/5, 10/7, 10/9) | Sequential Logic: Clocks, Latches, and Flip-Flops | Read/HW 07 | 10/11, 11:59PM |
| Week 8 (10/12, 10/14, 10/16) | Sequential Logic: Finite State Machines | Read/HW 08 | 10/18, 11:59PM |
| Week 9 (10/19, 10/21, 10/23) | Sequential Logic: Registers, Counters, Shifters | Read/HW 09 | 10/25, 11:59PM |
| Week 10 (10/26) | Sequential Logic: Arithmetic Logic Unit | – | – |
| Week 10 (10/28) | Midterm II Review | – | – |
| Week 10 (10/30) | Midterm II — In Person | – | – |
| Week 11 (11/2, 11/4, 11/6) | RTL: Register-Transfer Level Design | Read/HW 11 | 11/8, 11:59PM |
| Week 12 (11/9) | RTL: Register Memory Components and FIFO | Read/HW 12 | 11/15, 11:59PM |
| Week 12 (11/11) | NO INSTRUCTION — Veterans Day | – | – |
| Week 12 (11/13) | RTL: Register Memory Components and FIFO | – | – |
| Week 13 (11/16, 11/18, 11/20) | RTL: Optimizations and Tradeoffs | Read/HW 13 | 11/22, 11:59PM |
| Week 14 (11/23, 11/25) | RTL: Physical Implementation on ICs | Read/HW 14 | 11/29, 11:59PM |
| Week 14 (11/27) | NO INSTRUCTION — Thanksgiving Period | – | – |
| Week 15 (11/30, 12/2, 12/4) | RTL: Programmable Processors | Read/HW 15 | 12/6, 11:59PM |
| Week 16 (12/7, 12/9) | Review, Practice Final | Practice Final | – |
| Study Period (12/11–12/12) | Study Period | – | – |
| Finals (12/18) | Friday 12:00 – 2:00 pm | – | 12/18, 2:00PM |
Laboratory
| TIME | Materials | Virtual | DEADLINE |
|---|---|---|---|
| Week 1 (8/27) | Vivado Tutorial | Vlab 00 | 8/30, 11:59PM |
| Week 2 (9/3) | Modeling Concepts | Vlab 01 | 9/6, 11:59PM |
| Week 3 (9/10) | Numbering Systems | Vlab 02 | – |
| Week 4 (9/17) | Numbering Systems | Vlab 02 | 9/20, 11:59PM |
| Week 5 (9/24) | Multi-Output Circuits | Vlab 03 | – |
| Week 6 (10/1) | Multi-Output Circuits | Vlab 03 | 10/4, 11:59PM |
| Week 7 (10/8) | Tasks, Functions, and Testbench | Vlab 04 | 10/11, 11:59PM |
| Week 8 (10/15) | Modeling Latches and Flip-Flops | Vlab 05 | 10/18, 11:59PM |
| Week 9 (10/22) | Finite State Machines | Vlab 06 | – |
| Week 10 (10/29) | Finite State Machines | Vlab 06 | 11/1, 11:59PM |
| Week 11 (11/5) | Modeling Registers and Counters | Vlab 07 | 11/8, 11:59PM |
| Week 12 (11/12) | Behavioral Modeling and Timing Constraints | Vlab 09 | 11/15, 11:59PM |
| Week 13 (11/19) | Sequential System Design using ASM Charts | Vlab 10 | – |
| Week 14 (11/26) | NO INSTRUCTION — Thanksgiving | – | – |
| Week 15 (12/3) | Sequential System Design using ASM Charts | Vlab 10 | 12/6, 11:59PM |
| Week 16 (12/10) | Lab Completion | – | 12/10, 11:59PM |
The grading breakdown is subject to change at the discretion of the instructor and in accordance with the University grading system and policies. ↩︎