Systemverilog | Yao Zheng@UHMhttps://gustybear.github.io/tags/systemverilog/SystemverilogHugo Blox Builder (https://hugoblox.com)en-usMon, 10 Aug 2026 02:58:53 +0000https://gustybear.github.io/media/logo_hu_d0a0b1783c391ac0.pngSystemveriloghttps://gustybear.github.io/tags/systemverilog/ECE361: Digital Systems and Computer Designhttps://gustybear.github.io/teaching/course_ece361_2026_fall/Mon, 10 Aug 2026 02:58:53 +0000https://gustybear.github.io/teaching/course_ece361_2026_fall/<h1 id="executive-summary">Executive Summary</h1> <p>ECE 361 is an undergraduate-level course on computer organization and processor design. This course explores the fundamental organization and design of computer systems, starting from computer architecture and instruction set architecture (ISA), through processor datapath and control design, to arithmetic logic units (ALUs), memory organization, and input/output (I/O) systems. The course also introduces SystemVerilog for modeling, implementing, and testing processor components and computer systems, providing students with hands-on experience in hardware-oriented system design. Pre: 205 and 260, or consent.</p> <h1 id="logistics">Logistics</h1> <ul> <li> <p><strong>CRN</strong></p> <table> <thead> <tr> <th>ECE361 001</th> <th>ECE361L 001</th> <th>ECE361L 002</th> <th>ECE361L 003</th> </tr> </thead> <tbody> <tr> <td>77422</td> <td>77643</td> <td>77644</td> <td>77645</td> </tr> </tbody> </table> </li> <li> <p><strong>Personnel</strong></p> <table> <thead> <tr> <th>Role / Personnel</th> <th>Assigned Session</th> <th>Office Hours / Notes</th> </tr> </thead> <tbody> <tr> <td>Lecturer: </td> <td>N/A</td> <td>see </td> </tr> <tr> <td>TA: </td> <td>Session 1 (T 09:00am - 11:45am)</td> <td>TBD</td> </tr> <tr> <td>TA: </td> <td>Session 2 (T 13:30pm - 16:15pm)</td> <td>TBD</td> </tr> </tbody> </table> </li> <li> <p><strong>Classroom</strong></p> <table> <thead> <tr> <th>Time</th> <th>Location</th> <th>Textbook/HW</th> <th>HW/Exam Effort</th> </tr> </thead> <tbody> <tr> <td>MWF 09:30am-10:20am</td> <td>Holmes Hall 242</td> <td><em>Logic Design and Verification Using SystemVerilog (Revised)</em> by Donald Thomas</td> <td>Individual</td> </tr> <tr> <td></td> <td></td> <td><em>Computer Organization and Design: The Hardware/Software Interface — MIPS Edition</em> by Patterson and Hennessy</td> <td></td> </tr> </tbody> </table> </li> <li> <p><strong>Laboratory</strong></p> <table> <thead> <tr> <th>Session</th> <th>Time</th> <th>Location</th> <th>Report Effort</th> </tr> </thead> <tbody> <tr> <td>01</td> <td>T 09:00am - 11:45am</td> <td>Holmes Hall 451</td> <td>Group</td> </tr> <tr> <td>02</td> <td>T 13:30pm - 16:15pm</td> <td>Holmes Hall 451</td> <td>Group</td> </tr> </tbody> </table> </li> </ul> <h1 id="grading">Grading</h1> <ul> <li><strong>Breakdown</strong><sup id="fnref:1"><a href="#fn:1" class="footnote-ref" role="doc-noteref">1</a></sup></li> </ul> <table> <thead> <tr> <th>Midterm Exam 1</th> <th>Midterm Exam 2</th> <th>Final Exam</th> <th>Homeworks / Take-Home Quizzes</th> </tr> </thead> <tbody> <tr> <td>25%</td> <td>25%</td> <td>25%</td> <td>25%</td> </tr> </tbody> </table> <ul> <li><strong>Cutoffs</strong></li> </ul> <table> <thead> <tr> <th>A</th> <th>A-</th> <th>B+</th> <th>B</th> <th>B-</th> <th>C+</th> <th>C</th> <th>C-</th> <th>D+</th> <th>D</th> <th>D-</th> <th>F</th> </tr> </thead> <tbody> <tr> <td>90%</td> <td>87%</td> <td>83%</td> <td>80%</td> <td>77%</td> <td>73%</td> <td>70%</td> <td>67%</td> <td>63%</td> <td>60%</td> <td>57%</td> <td>&lt;57%</td> </tr> </tbody> </table> <ul> <li><strong>Proscribed Conduct</strong>: Copying or otherwise cheating on homework, lab reports, or exam will result in a failing grade for the course. More details can be found at student conduct code policies, </li> </ul> <h1 id="schedule">Schedule</h1> <h2 id="lecture">Lecture</h2> <h2 id="lecture-1">Lecture</h2> <table> <thead> <tr> <th>TIME</th> <th>TOPICS</th> <th>READING / HW / EXAM</th> <th>DEADLINE</th> </tr> </thead> <tbody> <tr> <td>Week 1 — Mon. 8/24/2026</td> <td>Introduction / Review Part 1: Data</td> <td>Data representation, conversions, signed integers, arithmetic</td> <td>&ndash;</td> </tr> <tr> <td>Week 1 — Wed. 8/26/2026</td> <td>Review Part 2: Logic Operations</td> <td>Logic operations and Boolean concepts</td> <td>&ndash;</td> </tr> <tr> <td>Week 1 — Fri. 8/28/2026</td> <td>Review Part 3: Combinational Circuits</td> <td>Combinational logic and circuit design</td> <td>&ndash;</td> </tr> <tr> <td>Week 2 — Mon. 8/31/2026</td> <td>Review Part 4: Sequential Circuits</td> <td>Sequential logic and state</td> <td>&ndash;</td> </tr> <tr> <td>Week 2 — Wed. 9/2/2026</td> <td>SystemVerilog I: Combinational Circuits</td> <td>SystemVerilog modeling of combinational circuits</td> <td>&ndash;</td> </tr> <tr> <td>Week 2 — Fri. 9/4/2026</td> <td>SystemVerilog I: Simulation</td> <td>Simulation and verification basics</td> <td>&ndash;</td> </tr> <tr> <td>Week 3 — Mon. 9/7/2026</td> <td><strong>NO INSTRUCTION — Labor Day</strong></td> <td>&ndash;</td> <td>&ndash;</td> </tr> <tr> <td>Week 3 — Wed. 9/9/2026</td> <td>SystemVerilog I: Sequential Circuits</td> <td>Sequential circuit modeling</td> <td>&ndash;</td> </tr> <tr> <td>Week 3 — Fri. 9/11/2026</td> <td>SystemVerilog I: Additional Constructs</td> <td>Additional SystemVerilog concepts</td> <td>&ndash;</td> </tr> <tr> <td>Week 4 — Mon. 9/14/2026</td> <td>Computer Architecture Overview I: Introduction and Performance</td> <td>Patterson &amp; Hennessy, Sec. 1.1–1.6</td> <td>&ndash;</td> </tr> <tr> <td>Week 4 — Wed. 9/16/2026</td> <td>Computer Architecture Overview II: Design</td> <td>Patterson &amp; Hennessy, Sec. 1.7–1.11</td> <td>&ndash;</td> </tr> <tr> <td>Week 4 — Fri. 9/18/2026</td> <td>ISA I: Barely C</td> <td>Programming model and preparation for MIPS ISA</td> <td>&ndash;</td> </tr> <tr> <td>Week 5 — Mon. 9/21/2026</td> <td>ISA II: CPU and Instruction Execution</td> <td>MIPS ISA</td> <td>&ndash;</td> </tr> <tr> <td>Week 5 — Wed. 9/23/2026</td> <td>ISA III</td> <td>MIPS instructions and data operations</td> <td>&ndash;</td> </tr> <tr> <td>Week 5 — Fri. 9/25/2026</td> <td>ISA IV: Instruction Formats</td> <td>MIPS instruction encoding and formats</td> <td>&ndash;</td> </tr> <tr> <td>Week 6 — Mon. 9/28/2026</td> <td>ISA V: Stack</td> <td>Stack organization and usage</td> <td>&ndash;</td> </tr> <tr> <td>Week 6 — Wed. 9/30/2026</td> <td>ISA Practice / Quiz / Problem Solving</td> <td>Review and practice</td> <td>&ndash;</td> </tr> <tr> <td>Week 6 — Fri. 10/2/2026</td> <td>ISA VI: Subroutines</td> <td>Procedure calls and subroutines</td> <td>&ndash;</td> </tr> <tr> <td>Week 7 — Mon. 10/5/2026</td> <td>ISA VII: System-Level Concepts</td> <td>System-level ISA concepts</td> <td>&ndash;</td> </tr> <tr> <td>Week 7 — Wed. 10/7/2026</td> <td>ISA Review / Problem Solving</td> <td>Review and practice</td> <td>&ndash;</td> </tr> <tr> <td>Week 7 — Fri. 10/9/2026</td> <td>Processor I: Single-Cycle Processor</td> <td>Single-cycle datapath and control</td> <td>&ndash;</td> </tr> <tr> <td>Week 8 — Mon. 10/12/2026</td> <td>Processor II: Pipeline</td> <td>Pipelining fundamentals</td> <td>&ndash;</td> </tr> <tr> <td>Week 8 — Wed. 10/14/2026</td> <td>Processor II: Pipeline, continued</td> <td>Pipeline stages and timing</td> <td>&ndash;</td> </tr> <tr> <td>Week 8 — Fri. 10/16/2026</td> <td>Processor III: Pipeline Implementation</td> <td>Pipelined datapath implementation</td> <td>&ndash;</td> </tr> <tr> <td>Week 9 — Mon. 10/19/2026</td> <td>Processor IV: Hazards</td> <td>Pipeline hazards</td> <td>&ndash;</td> </tr> <tr> <td>Week 9 — Wed. 10/21/2026</td> <td>Processor V: Data Hazards</td> <td><strong>Midterm Exam 1 — Take Home opens</strong></td> <td>12:01 AM</td> </tr> <tr> <td>Week 9 — Fri. 10/23/2026</td> <td>Processor VI: Control Hazards</td> <td>Branches and control hazards</td> <td>&ndash;</td> </tr> <tr> <td>Week 10 — Mon. 10/26/2026</td> <td>Processor VII: Dynamic Prediction</td> <td><strong>Midterm Exam 1 — Take Home due</strong></td> <td>11:59 PM</td> </tr> <tr> <td>Week 10 — Wed. 10/28/2026</td> <td>Memory I: Basics</td> <td>Memory hierarchy fundamentals</td> <td>&ndash;</td> </tr> <tr> <td>Week 10 — Fri. 10/30/2026</td> <td>Memory II: Blocks and Caches</td> <td>Cache blocks and mapping</td> <td>&ndash;</td> </tr> <tr> <td>Week 11 — Mon. 11/2/2026</td> <td>Cache and Memory Review</td> <td>Memory hierarchy review and practice</td> <td>&ndash;</td> </tr> <tr> <td>Week 11 — Wed. 11/4/2026</td> <td>Memory III: Technologies</td> <td>Memory technologies</td> <td>&ndash;</td> </tr> <tr> <td>Week 11 — Fri. 11/6/2026</td> <td>ALU I: Integer Arithmetic</td> <td>Integer arithmetic</td> <td>&ndash;</td> </tr> <tr> <td>Week 12 — Mon. 11/9/2026</td> <td>ALU II: Integer Multiplication</td> <td>Multiplication hardware and algorithms</td> <td>&ndash;</td> </tr> <tr> <td>Week 12 — Wed. 11/11/2026</td> <td><strong>NO INSTRUCTION — Veterans Day</strong></td> <td>&ndash;</td> <td>&ndash;</td> </tr> <tr> <td>Week 12 — Fri. 11/13/2026</td> <td>ALU III: Floating Point</td> <td>Floating-point representation and arithmetic</td> <td>&ndash;</td> </tr> <tr> <td>Week 13 — Mon. 11/16/2026</td> <td>ALU Review</td> <td>ALU review and practice</td> <td>&ndash;</td> </tr> <tr> <td>Week 13 — Wed. 11/18/2026</td> <td>Processor Review</td> <td>Processor, pipeline, memory, and ALU review</td> <td>&ndash;</td> </tr> <tr> <td>Week 13 — Fri. 11/20/2026</td> <td>Processor / Memory Review</td> <td>Review and problem solving</td> <td>&ndash;</td> </tr> <tr> <td>Week 14 — Mon. 11/23/2026</td> <td>SystemVerilog II: Hardware Threads and Clock Domains</td> <td><strong>Midterm Exam 2 — Take Home opens</strong></td> <td>12:01 AM</td> </tr> <tr> <td>Week 14 — Wed. 11/25/2026</td> <td>SystemVerilog II: Hardware Thread Interaction and Interfaces</td> <td>Thread interaction and interfaces</td> <td>&ndash;</td> </tr> <tr> <td>Week 14 — Fri. 11/27/2026</td> <td><strong>NO INSTRUCTION — Thanksgiving Period</strong></td> <td>&ndash;</td> <td>&ndash;</td> </tr> <tr> <td>Week 14 — Sun. 11/29/2026</td> <td>&ndash;</td> <td><strong>Midterm Exam 2 — Take Home due</strong></td> <td>11:59 PM</td> </tr> <tr> <td>Week 15 — Mon. 11/30/2026</td> <td>SystemVerilog III: Testbenches and Randomization</td> <td>Verification testbenches and constrained randomization</td> <td>&ndash;</td> </tr> <tr> <td>Week 15 — Wed. 12/2/2026</td> <td>SystemVerilog III: Assertions and Sequences</td> <td>Assertions, properties, and sequences</td> <td>&ndash;</td> </tr> <tr> <td>Week 15 — Fri. 12/4/2026</td> <td>I/O: Introduction</td> <td>I/O fundamentals and system integration</td> <td>&ndash;</td> </tr> <tr> <td>Week 16 — Mon. 12/7/2026</td> <td>I/O: Applications and Examples</td> <td>I/O applications and design examples</td> <td>&ndash;</td> </tr> <tr> <td>Week 16 — Wed. 12/9/2026</td> <td>Final Review</td> <td>Comprehensive final review</td> <td>&ndash;</td> </tr> <tr> <td>Study Period — 12/11/2026–12/12/2026</td> <td><strong>Study Period</strong></td> <td>&ndash;</td> <td>&ndash;</td> </tr> <tr> <td>Finals — Mon. 12/14/2026</td> <td><strong>Final Exam — In Person</strong></td> <td>Comprehensive Final Exam</td> <td>9:45–11:45 AM</td> </tr> </tbody> </table> <blockquote class="border-l-4 border-neutral-300 dark:border-neutral-600 pl-4 italic text-neutral-600 dark:text-neutral-400 my-6"> <p><strong>Note:</strong> Lecture topics are organized from the provided ECE361 slide set. Midterm placement follows the natural gaps and review material in that sequence; adjust the two midterm dates if the official Fall 2026 exam plan differs.</p> </blockquote> <h2 id="laboratory">Laboratory</h2> <h1 id="lab-schedule">Lab Schedule</h1> <table> <thead> <tr> <th>TIME</th> <th>LAB</th> <th>TOPIC</th> <th>DEADLINE</th> </tr> </thead> <tbody> <tr> <td>Week 1–2 — 8/25–9/8/2026</td> <td>1</td> <td>Unix/Linux</td> <td>9/8, 11:59 PM</td> </tr> <tr> <td>Week 3–4 — 9/8–9/22/2026</td> <td>2</td> <td>C Language</td> <td>9/22, 11:59 PM</td> </tr> <tr> <td>Week 5–6 — 9/22–10/6/2026</td> <td>3</td> <td>SystemVerilog I</td> <td>10/6, 11:59 PM</td> </tr> <tr> <td>Week 7–8 — 10/6–10/20/2026</td> <td>4</td> <td>QtSPIM and MIPS</td> <td>10/20, 11:59 PM</td> </tr> <tr> <td>Week 9–10 — 10/20–11/3/2026</td> <td>5</td> <td>FPGA</td> <td>11/3, 11:59 PM</td> </tr> <tr> <td>Week 11–12 — 11/3–11/17/2026</td> <td>6</td> <td>CPU Research</td> <td>11/17, 11:59 PM</td> </tr> <tr> <td>Week 13–15 — 11/17–12/8/2026</td> <td>7</td> <td>Pipeline Processor</td> <td>12/8, 11:59 PM</td> </tr> </tbody> </table> <div class="footnotes" role="doc-endnotes"> <hr> <ol> <li id="fn:1"> <p>The grading breakdown is subject to change at the discretion of the instructor and in accordance with the University grading system and policies.&#160;<a href="#fnref:1" class="footnote-backref" role="doc-backlink">&#x21a9;&#xfe0e;</a></p> </li> </ol> </div>