EE260 (Spring, 2026) | Yao Zheng@UHM

Take-Home Midterm Exam: Combinational Logic and Advanced Verilog

Fri, 27 Feb 2026 00:00:00 +0000

Scope: Number systems, Boolean algebra, multi-level optimization, hazards, arithmetic circuits, encoder/decoder/PLA/ROM, scalable MUX structures, parameterized Verilog
Duration: 48 hours

Instructions

Attempt all questions. Show complete derivations and clearly state assumptions.
Provide commented, synthesizable Verilog and a self-checking testbench where requested.
Include timing and area reasoning (gate depth, gate count, or asymptotic arguments).
No collaboration. Cite any references consulted.

Part A — Multiple Choice (10 × 3 = 30 pts)

Select the best answer.

Q1. Which transformation always preserves functional equivalence but may reduce logic depth?
a) Converting SOP to canonical SOP
b) Algebraic factoring
c) Expanding minterms
d) Adding consensus terms

Q2. A static-1 hazard occurs when:
a) Output should remain 1 but temporarily glitches to 0
b) Output should remain 0 but glitches to 1
c) Clock frequency is too high
d) Fan-out exceeds limit

Q3. For an N-bit ripple carry adder, worst-case delay is proportional to:
a) log₂N
b) N
c) √N
d) constant

Q4. Which gate set is functionally complete?
a) {XOR}
b) {AND, OR}
c) {NAND}
d) {XNOR}

Q5. In synthesizable combinational Verilog, the safest template is:
a) always @(posedge clk)
b) always @(*)
c) initial begin
d) #5 y = a & b;

Q6. A 16→1 multiplexer implemented as a balanced tree of 2→1 MUXes has depth:
a) 4
b) 8
c) 15
d) 16

Q7. ROM implementation size grows:
a) Linearly with inputs
b) Quadratically with inputs
c) Exponentially with inputs
d) Logarithmically with inputs

Q8. The consensus term of \(A'B + AC\) is:
a) BC
b) B’C
c) AB
d) A’C

Q9. Which operator performs bitwise XNOR in Verilog?
a) ~^
b) ^~
c) Both
d) None

Q10. A balanced adder tree reduces delay complexity from O(N) to:
a) O(1)
b) O(log N)
c) O(N²)
d) O(N log N)

Part B — Design & Analysis (10 × 7 = 70 pts)

Problem 1 — Multi-Level Optimization and Cost Analysis
Given
\(F(A,B,C,D,E)=\Sigma(1,3,4,7,11,15,16,18,19,23,27,31)\)

a) Write canonical SOP and POS.
b) Minimize using K-map.
c) Factor to reduce depth.
d) Compare literal count and logic depth between two-level and factored implementations.

Problem 2 — Hazard Analysis
Given
\(F(A,B,C)=A'B+AC\)

a) Identify static hazards and show transition causing glitch.
b) Add minimal consensus terms to eliminate hazard.
c) Estimate glitch width assuming uniform 1 ns gate delay.

Problem 3 — NAND-Only Realization
a) Prove NAND is functionally complete.
b) Implement \(F(A,B,C)=AB+A'C\) using only 2-input NAND gates.
c) Count gates and compute logic depth.

Problem 4 — 32→5 Priority Encoder
a) Define truth table with D31 highest priority and valid.
b) Build hierarchically from 4→2 encoders.
c) Structural Verilog implementation.
d) Estimate worst-case delay if each 4→2 block delay = 2 ns.

Problem 5 — Shared PLA vs ROM Implementation
Given
\(F_1=\Sigma(0,2,5,8,10,13)\)
\(F_2=\Sigma(1,3,6,9,14,15)\)

a) Minimize jointly and identify shared product terms.
b) Draw PLA matrix (AND plane and OR plane).
c) Determine memory size for equivalent 16×2 ROM.
d) Compare area tradeoffs.

Problem 6 — Balanced Adder Tree
Sum eight 12-bit numbers.

a) Serial ripple accumulation: compute depth.
b) Balanced tree: draw structure and compute depth.
c) Determine required output width.

Problem 7 — Parameterized ALU

Operations: ADD, SUB, AND, OR, XOR, CMP(==,>,<). Width parameter N.

a) Write synthesizable Verilog using unique case.
b) Implement comparison efficiently (no redundant subtraction).
c) Provide self-checking randomized testbench.
d) Compare resource growth for N=8 and N=32.

Problem 8 — Recursive MUX Tree

a) Implement a parameterized mux_tree #(N=16,W=8) using generate.
b) Ensure balanced structure.
c) Derive logic depth as function of N.
d) Provide synthesizable code.

Problem 9 — Gray/Binary Converters

a) Derive 4-bit Gray→Binary and Binary→Gray equations.
b) Prove composition correctness.
c) Provide parameterized Verilog and exhaustive testbench.

Problem 10 — Power-of-Two Detector

Design combinational circuit to detect if a 16-bit input is a power of two.

a) Derive minimal Boolean condition.
b) Implement structural and behavioral Verilog versions.
c) Compare gate complexity.

Take-Home Midterm Exam: Sequential Circuits and Verilog

Tue, 28 Oct 2025 00:00:00 +0000

Scope: Sequential logic, finite state machines, registers, counters, with Verilog modeling
Duration: 48 hours
Instructions

Attempt all questions. Show reasoning, derivations, and clearly state assumptions.
Provide commented, synthesizable Verilog and a self‑checking testbench where requested.
Include brief timing/area reasoning (big‑O style or gate/count estimates).
No collaboration. Cite any external references you consulted.
Tutorial of Online tools for Verilog simulation can be found .

Part A — Multiple Choice (10 × 3 pts = 30 pts)

Select the best answer.

Q1. Why are edge-triggered flip-flops preferred over level-sensitive latches in synchronous systems?
A. They reduce power consumption
B. They eliminate race-through conditions
C. They operate at higher frequency inherently
D. They require fewer transistors

Q2. A setup time violation occurs when:
A. Data arrives too early before the clock edge
B. Data arrives too late before the clock edge
C. Data changes too slowly
D. Clock period is too long

Q3. Which of the following circuits is most prone to metastability?
A. Combinational logic
B. Single flip-flop sampling asynchronous input
C. Synchronous counter
D. Registered pipeline

Q4. In a synchronous design, increasing combinational delay between registers will:
A. Increase hold margin
B. Reduce maximum clock frequency
C. Improve timing robustness
D. Eliminate hazards

Q5. A Moore FSM is generally more stable than a Mealy FSM because:
A. It uses fewer states
B. Outputs depend only on registered state
C. It requires no combinational logic
D. It runs at lower frequency

Q6. Which condition most directly causes a hold time violation?
A. Data path too slow
B. Data path too fast
C. Clock period too long
D. Setup time too large

Q7. Consider the Verilog snippet:

always @(posedge clk) begin
 q = d;
end

What is the main issue?
A. Non-synthesizable
B. Blocking assignment may cause incorrect sequential behavior
C. Missing sensitivity list
D. No issue

Q8. Consider:

always @(posedge clk) begin
 if (en)
 q <= d;
end

If en = 0, what happens to q?
A. Becomes 0
B. Becomes unknown
C. Holds previous value
D. Toggles

Q9. Which Verilog construct correctly models a synchronous reset flip-flop?
A.

always @(posedge clk or posedge rst)

always @(posedge clk)

always @(*)

D. Both A and B

Q10. In FSM coding, separating state register and next-state logic helps:
A. Reduce power only
B. Improve readability and avoid unintended latches
C. Increase clock frequency directly
D. Eliminate combinational logic

Part B — Sequential Design, Analysis, and Schematic (10 × 7 = 70 pts)

Problem 1 — Hazard Propagation into Sequential Logic

Given combinational logic feeding a flip-flop:

\(F = A'B + AB'\)

a) Determine whether a static-1 hazard exists. Justify using Boolean reasoning
b) Draw a timing diagram where input transitions cause a glitch
c) Explain how this glitch can be captured by a flip-flop
d) Modify the logic to eliminate the hazard and draw the corrected schematic
e) Explain why hazard removal is critical in synchronous pipelines

Problem 2 — Multi-Cycle Pulse Generator

Design a synchronous circuit that generates an output pulse of exactly 4 clock cycles upon detecting a rising edge on input x.

a) Define the required states and draw the FSM diagram
b) Provide a complete state transition table
c) Derive next-state equations
d) Draw the full schematic (flip-flops + combinational logic)
e) Describe behavior if x is asserted again during the active pulse

Problem 3 — Self-Correcting Mod-6 Counter

Design a synchronous mod-6 counter (0–5) that recovers automatically from invalid states.

a) Draw the state transition diagram including invalid states
b) Specify recovery transitions
c) Choose a state encoding and justify
d) Derive next-state logic equations
e) Draw the complete schematic
f) Explain why self-correction is important in real hardware

Problem 4 — Sequence Detector with Overlap and Reset

Design an FSM that detects the sequence 1101 with overlap allowed.

a) Draw the state diagram (minimal states)
b) Provide the state transition table
c) Derive output logic for a Mealy implementation
d) Convert to a Moore implementation
e) Compare:

output timing
number of states
f) Add a synchronous reset and explain its effect

Problem 5 — Timing Closure and Pipeline Insertion

A sequential circuit has:

t_clk-q = 1 ns
t_comb = 10 ns
t_setup = 2 ns

a) Compute the minimum clock period and maximum frequency
b) Determine if the design meets a 100 MHz requirement
c) Insert one pipeline stage and redraw the system
d) Recompute timing after pipelining
e) Discuss:

latency increase
throughput improvement
design tradeoffs

Problem 6 — Serial Pattern Detection: Architecture Comparison

Design a system to detect five consecutive 1s in a serial bitstream.

a) Implement using a shift register approach (block diagram)
b) Implement using an FSM approach (state diagram)
c) Compare:

hardware cost
detection latency
scalability for longer patterns
d) Explain which design is preferred in ASIC vs FPGA contexts

Problem 7 — Reliable Clock Domain Crossing (CDC)

Design a system to safely transfer an 8-bit data word between two clock domains.

a) Explain why a simple 2-FF synchronizer is insufficient
b) Draw a handshake-based CDC architecture
c) Provide a timing diagram showing req/ack interaction
d) Explain how data integrity and ordering are preserved
e) Discuss limitations of this approach

Problem 8 — Glitch-Free Output Design

An FSM controls a critical signal that must never glitch.

a) Explain why Mealy outputs may produce glitches
b) Convert a Mealy FSM into a glitch-free Moore FSM
c) Draw schematic with registered outputs
d) Analyze timing impact (one-cycle delay, stability)
e) Discuss when Mealy design is still preferred

Problem 9 — Sequential Resource Sharing

Design a system to compute:

\(Y = A + B + C + D\)

using a single adder reused over multiple cycles.

a) Draw the datapath (registers, muxes, adder)
b) Design the control FSM (states and transitions)
c) Provide a cycle-by-cycle execution table
d) Compare with parallel implementation:

area
latency
throughput
e) Explain when sequential reuse is advantageous

Problem 10 — Fair Traffic Controller with Priority and Starvation Avoidance

Design a traffic controller with:

Main road (high priority)
Side road (low priority)
Pedestrian request input

a) Define system states and timing requirements
b) Draw FSM diagram
c) Explain how priority is enforced for main road
d) Design a mechanism to prevent starvation of side road and pedestrians
e) Ensure all transitions are safe (no conflicting greens)
f) Discuss how the design can scale to more lanes or intersections

Practice Final Exam

Fri, 08 May 2026 00:00:00 +0000

weight: 5

ECE 260 — Practice Final Exam (2 Hours)

Course: ECE 260 Introduction to Digital Design
Duration: 2 Hours
Coverage:

Combinational Logic
Sequential Logic
FSM Design
RTL Design
Pipelines and Hazards
Cache and Memory Hierarchy
RISC Pipelines
Out-of-Order Processors

Part A — Multiple Choice (15 × 2 pts = 30 pts)

Select the best answer.

Q1.

A structural hazard occurs when:

A. Two pipeline stages require the same hardware resource
B. A branch instruction changes PC
C. The clock frequency is too high
D. A cache miss occurs

Solution: A
Structural hazards occur due to hardware resource conflicts.

Q2.

Which memory technology is typically used for CPU cache?

A. DRAM
B. SRAM
C. Flash
D. EEPROM

Solution: B
SRAM is faster and used for cache.

Q3.

A Moore FSM output depends on:

A. Inputs only
B. Current state only
C. Inputs and outputs
D. Clock frequency

Solution: B

Q4.

Forwarding in a pipeline mainly reduces:

A. Structural hazards
B. RAW hazards
C. WAR hazards
D. WAW hazards

Solution: B

Q5.

Which cache organization generally has the fewest conflict misses?

A. Direct mapped
B. 2-way set associative
C. Fully associative
D. Write-through

Solution: C

Q6.

A barrel shifter is primarily built from:

A. Adders
B. Flip-flops
C. Multiplexers
D. Decoders

Solution: C

Q7.

In Verilog, nonblocking assignment uses:

A. =
B. <=
C. ==
D. :=

Solution: B

Q8.

The maximum clock frequency of a processor is determined by:

A. Shortest path delay
B. Critical path delay
C. Number of registers
D. Cache size

Solution: B

Q9.

A. RAW hazards
B. WAR and WAW hazards
C. Cache hazards
D. Structural hazards

Solution: B

Q10.

Which pipeline hazard is caused by branch instructions?

A. RAW
B. Structural
C. Control
D. WAW

Solution: C

Q11.

A flip-flop updates state on:

A. Logic transitions only
B. Clock edge
C. Input enable
D. Reset signal only

Solution: B

Q12.

The reorder buffer (ROB) is mainly used in:

A. FSM controllers
B. Sequential datapaths
C. Out-of-order processors
D. SRAM arrays

Solution: C

Q13.

Spatial locality means:

A. Recently used data reused soon
B. Nearby memory locations likely accessed
C. Instructions always sequential
D. Data stored in cache forever

Solution: B

Q14.

Which stage performs arithmetic operations in a classic RISC pipeline?

A. IF
B. ID
C. EX
D. WB

Solution: C

Q15.

Pipeline throughput improves because:

A. Instructions execute simultaneously
B. Clock frequency becomes zero
C. Pipeline removes all hazards
D. Cache misses disappear

Solution: A

Part B — Design and Analysis (10 × 7 pts = 70 pts)

Problem 1 — Sequence Detector FSM

Design a Moore FSM that detects the sequence:

1011

Overlapping sequences should be detected.

(a)

Draw the state diagram.

(b)

Define the state transition table.

(c)

Indicate which state produces output = 1.

(d)

Explain why a Moore FSM output changes more predictably than a Mealy FSM.

Solution

(a) States

S0 = initial
S1 = detected 1
S2 = detected 10
S3 = detected 101
S4 = detected 1011

(b) Example transitions

S0 –1→ S1
S1 –0→ S2
S2 –1→ S3
S3 –1→ S4

Overlapping:

S4 –0→ S2
S4 –1→ S1

(c)

Output = 1 only in S4.

(d)

Moore outputs depend only on registered state, so outputs change only on clock edges.

Problem 2 — RTL Datapath Design

Implement:

if (SEL == 0) X ← A + B else X ← A − B

(a)

Draw the datapath.

(b)

Identify required components.

(c)

Show control signals.

(d)

Explain how subtraction can be implemented using an adder.

Solution

(a) Datapath

Components:

Register A
Register B
ALU
X register
Control line SEL

(b)

Required hardware:

Adder/Subtractor
XOR bank for B inversion
Carry-in control

(c)

SEL=0 → addition
SEL=1 → subtraction

(d)

A - B = A + (~B) + 1

Uses two’s complement arithmetic.

Problem 3 — Pipeline Hazard Analysis

Given:

ADD R1,R2,R3 SUB R4,R1,R5 AND R6,R4,R7

(a)

Identify all RAW hazards.

(b)

Show where forwarding occurs.

(c)

Determine if stalls are required.

(d)

Explain how forwarding improves performance.

Solution

(a)

Hazards:

SUB depends on ADD
AND depends on SUB

(b)

Forward:

ADD EX/MEM → SUB EX
SUB EX/MEM → AND EX

(c)

No stalls if forwarding hardware exists.

(d)

Forwarding bypasses waiting for WB stage.

Problem 4 — Cache Design

Compare:

Direct mapped
2-way set associative
Fully associative

(a)

Draw organization of each.

(b)

Compare hardware complexity.

(c)

Compare conflict misses.

(d)

Which provides best performance and why?

Solution

Direct mapped

Simplest
Fastest indexing
Highest conflict misses

2-way set associative

Better balance
Moderate complexity

Fully associative

Lowest conflict misses
Requires many comparators

Best overall practical choice: 2-way or 4-way associative.

Problem 5 — Register File

Design a register file with:

8 registers
2 read ports
1 write port

(a)

Draw block diagram.

(b)

Explain read operation.

(c)

Explain write operation.

(d)

Describe required decoders and multiplexers.

Solution

(a)

Components:

8 registers
Write decoder
Two read MUXes

(b)

Read ports select registers simultaneously.

(c)

Write decoder activates one register enable.

(d)

3-to-8 decoder
Two 8-to-1 MUXes

Problem 6 — Barrel Shifter

Design a 4-bit rotate-left barrel shifter.

(a)

Show all possible rotations.

(b)

Draw multiplexer stages.

(c)

Determine number of multiplexers required.

(d)

Explain why barrel shifters are faster than iterative shifters.

Solution

(a)

Possible rotations:

(b)

Two-stage MUX network:

Shift by 1
Shift by 2

(c)

Requires:

8 multiplexers total

(d)

All shifts occur in parallel combinational hardware.

Problem 7 — Five-Stage RISC Pipeline

(a)

Draw the 5 stages.

(b)

Describe purpose of each stage.

(c)

Indicate where hazards occur.

(d)

Explain why pipelining improves throughput.

Solution

Pipeline:

IF → ID → EX → MEM → WB

IF

Fetch instruction.

ID

Decode + register read.

EX

ALU operation.

MEM

Memory access.

WB

Write register.

Hazards:

RAW in EX
Control hazards after branch

Throughput improves by overlapping execution.

Problem 8 — Branch Prediction

(a)

Explain static branch prediction.

(b)

Explain dynamic branch prediction.

(c)

Why do mispredictions hurt performance?

(d)

What hardware is commonly used in dynamic prediction?

Solution

Static

Fixed guess.

Dynamic

Uses runtime history.

Misprediction penalty

Pipeline flush required.

Hardware

Branch history table
Saturating counters

Problem 9 — Out-of-Order Processor

Explain:

(a)

Issue Queue

(b)

Reorder Buffer

(c)

(d)

Why OoO processors achieve higher performance.

Solution

Issue Queue

Stores ready instructions.

ROB

Commits instructions in-order.

Register Renaming

Removes false dependencies.

Higher performance

Allows independent instructions to execute earlier.

Problem 10 — Iterative Multiplier

Given:

if (B[0] == 1) P ← P + A

A ← A « 1 B ← B » 1

(a)

Draw datapath.

(b)

Identify registers.

(c)

Draw FSM states.

(d)

Explain why multiplication requires multiple cycles.

Solution

(a)

Datapath:

Adder
Shift register A
Shift register B
Product register P

(b)

Registers:

A
B
P
Counter

(c)

FSM:

IDLE
CHECK
ADD
SHIFT
DONE

(d)

Each bit of multiplier processed sequentially.

Complexity:

N-bit multiplication requires N cycles.