EE260 (Fall, 2025) | Yao Zheng@UHM

Take-Home Midterm Exam: Combinational Circuits and Verilog

Tue, 30 Sep 2025 00:00:00 +0000

Scope: Number systems, Boolean algebra, combinational design, optimization, hazards, MUX/decoder/PLA, Verilog HDL
Duration: 48 hours
Instructions

Attempt all questions. Show reasoning, derivations, and clearly state assumptions.
Provide commented, synthesizable Verilog and a self‑checking testbench where requested.
Include brief timing/area reasoning (big‑O style or gate/count estimates).
No collaboration. Cite any external references you consulted.

Part A — Multiple Choice (10 × 3 = 30 pts)

Select the best answer.

Q1. Which of the following is not a characteristic of combinational logic?
a) Output depends only on present inputs
b) No feedback paths
c) May exhibit propagation delay
d) Requires clock edge to update

Q2. Which Verilog statement is not synthesizable in general FPGA/ASIC tools?
a) assign y = a & b;
b) always @(*) y = a | b;
c) initial y = 0;
d) case(sel) y = d0; endcase

Q3. The critical path delay in a ripple‑carry adder grows:
a) Linearly with bit‑width
b) Logarithmically with bit‑width
c) Constant with bit‑width
d) Randomly with input values

Q4. Which gate set is not functionally complete?
a) {NAND}
b) {NOR}
c) {AND, OR}
d) {XOR, AND}

Q5. In Verilog, reg and wire differ because:
a) reg can only be used in sequential circuits
b) wire holds values without drivers
c) reg stores a value until reassigned; wire reflects drivers continuously
d) wire is faster than reg

Q6. A 32‑to‑1 multiplexer can be implemented most efficiently using:
a) One 32‑input gate
b) A tree of 2‑to‑1 multiplexers
c) A PLA
d) Multiple XOR gates

Q7. Which optimization reduces logic depth the most?
a) Gate duplication
b) Pipelining
c) Karnaugh map simplification
d) Multi‑level factoring

Q8. Which Verilog operator performs bitwise XNOR?
a) ~^
b) ^~
c) Both a and b
d) None

Q9. Main limitation of ROM implementation for logic functions is:
a) Too slow for combinational circuits
b) Size grows exponentially with #inputs
c) Can only implement sequential logic
d) Does not support initialization

Q10. If two drivers assign conflicting values to a Verilog wire:
a) Last assignment wins
b) Wire holds 0
c) Wire holds 1
d) Wire becomes unknown (x)

Part B — Design & Analysis (10 × 7 = 70 pts)

Problem 1 — Functional Completeness (NAND‑Only)
a) Prove {NAND} is functionally complete (construct NOT, AND, OR).
b) Implement $F(A,B,C)=\Sigma(0,2,5,7)$ using NAND‑only. Show product terms and sharing.
c) Provide synthesizable Verilog for the NAND‑only implementation and compare gate count v.s. SOP using AND/OR/NOT.

Problem 2 — Arithmetic: Carry‑Save Adder (CSA)
a) Derive a 3‑operand (A,B,C) 4‑bit CSA producing (Sum, Carry).
b) Compare worst‑case delay against 2‑operand ripple add repeated twice.
c) Provide synthesizable Verilog for a parameterized CSA.

Problem 3 — 16→4 Priority Encoder
a) Specify truth table/priority convention (D$15$ highest). Include valid.
b) Build hierarchically from 4×(4→2) encoders + 4→2 encoder.
c) Structural Verilog with module instances.

Problem 4 — PLA and ROM Implementations
Given:
$F_1(A,B,C,D)=\Sigma(0,2,5,8,12),\quad F_2(A,B,C,D)=\Sigma(1,3,4,9,15)$
a) Derive minimized SOPs with shared product terms for a PLA.
b) Sketch a PLA with labeled shared products.
c) Show 16×2 ROM mapping (address=A B C D).
d) Provide generic Verilog: (i) PLA using and of literals + or planes; (ii) ROM using case or packed localparam.

Problem 5 — Scalable MUX
a) Build a 16→1 MUX using only 2→1 MUXes (balanced tree).
b) Count 2→1 cells and tree depth.
c) Write a parameterized recursive Verilog module mux_tree #(N=16,W=1).

Problem 6 — Comparator (4‑bit)
a) Derive equations for GT, EQ, LT.
b) Show hierarchical design from chained 1‑bit comparators.
c) Provide synthesizable Verilog and a constrained‑random testbench.

Problem 7 — Gray/Binary Converters (4‑bit)
a) Derive equations: Gray→Bin and Bin→Gray.
b) Compose them in loopback to prove Bin == g2b(b2g(Bin)).
c) Parameterized Verilog + exhaustive testbench.

Problem 8 — Digital Lock
Opens for inputs 110101 or 011110.
a) Minimize SOP.
b) Implement via decoder + OR.
c) Verilog (behavioral and structural).
d) Short note: why loose “don’t care” policies are risky for security.

Problem 9 — Parameterized ALU
Ops: ADD, SUB, AND, OR, XOR, CMP(==,>,<). Width parameter N.
a) Synthesizable Verilog with unique case.
b) Self‑checking randomized testbench (seeded).
c) Brief resource discussion for N=8 vs N=32 (qualitative + simple count).

Problem 10 — Adder Tree
Sum eight 16‑bit numbers with minimal depth.
a) Draw balanced adder tree and give depth.
b) Compare with serial accumulation.
c) Parameterized Verilog using generate and a reduction tree.

Take-Home Midterm Exam Solution: Combinational Circuits and Verilog

Tue, 30 Sep 2025 00:00:00 +0000

Scope: Number systems, Boolean algebra, combinational design, optimization, hazards, MUX/decoder/PLA, Verilog HDL
Duration: 48 hours
Instructions

Attempt all questions. Show reasoning, derivations, and clearly state assumptions.
Provide commented, synthesizable Verilog and a self‑checking testbench where requested.
Include brief timing/area reasoning (big‑O style or gate/count estimates).
No collaboration. Cite any external references you consulted.

Part A — Multiple Choice (Keys)

Part B — Design & Analysis

Problem 1 — Functional Completeness (NAND‑Only)

a) Constructions

NOT: $ \neg A = A\,\text{NAND}\,A $
AND: $ A\land B = (A\,\text{NAND}\,B)\,\text{NAND}\,(A\,\text{NAND}\,B) $
OR (by De Morgan): $ A\lor B = (\neg A)\,\text{NAND}\,(\neg B) = (A\,\text{NAND}\,A)\,\text{NAND}\,(B\,\text{NAND}\,B) $

b) Minimal SOP for $F=\Sigma(0,2,5,7)$ → $F = A' C' + A C$. (Covers 0,2 and 5,7.)

c) NAND‑only Verilog

module F_nand_only(input A,B,C, output F);
 wire nA, nC, t1, t2; // B not used after minimization
 nand (nA, A, A);
 nand (nC, C, C);
 wire nA_and_nC, AbarCbar;
 nand (nA_and_nC, nA, nC);
 nand (AbarCbar, nA_and_nC, nA_and_nC);
 wire AandC_n, AandC;
 nand (AandC_n, A, C);
 nand (AandC, AandC_n, AandC_n);
 wire nAbarCbar, nAandC;
 nand (nAbarCbar, AbarCbar, AbarCbar);
 nand (nAandC, AandC, AandC);
 nand (F, nAbarCbar, nAandC);
endmodule

Gate count ~7 NANDs.

Problem 2 — CSA

Sum bits: $s_i = a_i \oplus b_i \oplus c_i$, carry bits: $k_i=(a_ib_i)+(b_ic_i)+(a_ic_i)$. Final result = s + (k<<1) via one CPA. Delay better than two ripples.

module csa3 #(parameter N=4)(input [N-1:0] a,b,c,
 output [N-1:0] s, output [N-1:0] k);
 genvar i;
 generate for(i=0;i<N;i=i+1) begin: g
 assign s[i]=a[i]^b[i]^c[i];
 assign k[i]=(a[i]&b[i])|(b[i]&c[i])|(a[i]&c[i]);
 end endgenerate
endmodule

Problem 3 — 16→4 Priority Encoder

See hierarchical structural solution:

module pe4(input [3:0] d, output valid, output [1:0] y);
 assign valid = |d;
 assign y = !valid ? 2'b00 :
 d[3] ? 2'b11 :
 d[2] ? 2'b10 :
 d[1] ? 2'b01 : 2'b00;
endmodule

module pe16(input [15:0] d, output valid, output [3:0] y);
 wire [3:0] v; wire [1:0] y0,y1,y2,y3;
 pe4 u0(d[3:0], v[0], y0);
 pe4 u1(d[7:4], v[1], y1);
 pe4 u2(d[11:8], v[2], y2);
 pe4 u3(d[15:12], v[3], y3);
 pe4 uT(v, valid, y[3:2]);
 reg [1:0] low;
 always @(*) case(y[3:2])
 2'd0: low=y0; 2'd1: low=y1; 2'd2: low=y2; default: low=y3;
 endcase
 assign y[1:0]=low;
endmodule

Problem 4 — PLA & ROM

One valid sharing (not unique):

$F_1 = A'B' + C'D' + AD'$
$F_2 = A'CD + AB' + B'D$

PLA code shown (shared terms). ROM mapping by full truth table is acceptable (example mapping provided in handout).

Problem 5 — Scalable MUX

Uses $N-1$ 2→1 cells; for 16→1, 15 cells, depth 4. Recursive mux_tree given in handout; students verify widths and $clog2 correctness with synthesis/sim.

Problem 6 — Comparator

Equations:
EQ = Π_i ~(Ai ^ Bi)
GT = g3 | (eq3&g2) | (eq3&eq2&g1) | (eq3&eq2&eq1&g0)
LT mirror. Verilog in handout accepted.

Problem 7 — Gray/Binary

Gray→Bin prefix XOR; Bin→Gray adjacent XOR. Parameterized modules and exhaustive TB as shown.

Problem 8 — Lock

assign open = (in==6'b110101) || (in==6'b011110);
Security note: define all unspecified inputs as closed (0); avoid ‘x’ in synthesizable paths.

Problem 9 — ALU

Reference ALU with unique case. TB randomizes A,B and compares against high‑level model. Resource: adder dominates; scaling roughly linear with N for ripple implementations.

Problem 10 — Adder Tree

Balanced tree depth 3 for 8 inputs; serial is 7. Example parameterized module provided; students may generalize to 2^k inputs or pad to nearest power of two.

module sum8 #(parameter W=16)(input [W-1:0] a0,a1,a2,a3,a4,a5,a6,a7,
 output [W+3:0] sum);
 wire [W:0] s0=a0+a1, s1=a2+a3, s2=a4+a5, s3=a6+a7;
 wire [W+1:0] t0=s0+s1, t1=s2+s3;
 assign sum = t0 + t1;
endmodule

Take-Home Midterm Exam: Sequential Circuits and Verilog

Tue, 28 Oct 2025 00:00:00 +0000

Scope: Sequential logic, finite state machines, registers, counters, with Verilog modeling
Duration: 48 hours
Instructions

Attempt all questions. Show reasoning, derivations, and clearly state assumptions.
Provide commented, synthesizable Verilog and a self‑checking testbench where requested.
Include brief timing/area reasoning (big‑O style or gate/count estimates).
No collaboration. Cite any external references you consulted.
Tutorial of Online tools for Verilog simulation can be found .

Part A — Multiple Choice (10 × 3 pts = 30 pts)

Select the best answer.

Q1. A positive-level D latch is best described as:

A. Sampling on rising edges only
B. Transparent when clock=1 and opaque when clock=0
C. Triggered on both edges
D. Metastability-free by design

Q2. The parameter that primarily limits f_max is:

A. Hold time
B. Recovery time
C. t_clk-q + t_comb + t_setup
D. Clock duty cycle

Q3. A T flip-flop divides the clock by two because it:

A. Filters every other edge by delay
B. Toggles its output at each active edge
C. Samples input twice per cycle
D. Has J=0, K=1

Q4. A ripple counter differs from a synchronous counter because:

A. It uses fewer flip-flops
B. Its stages are clocked by preceding stage outputs
C. It is immune to propagation delay
D. It is always faster

Q5. In a Moore machine, outputs depend on:

A. Current input only
B. Current state only
C. Next state only
D. Current and previous inputs

Q6. In a Mealy machine:

A. Outputs change only at clock edges
B. Outputs depend on state and inputs
C. It needs more states than Moore always
D. It cannot be coded in Verilog

Q7. A 4-bit shift register with serial input 1101 after four clocks contains (MSB..LSB):

A. 1011
B. 1101
C. 0110
D. 1110

Q8. A hold-time violation can be mitigated by:

A. Adding delay to data path
B. Increasing clock frequency
C. Reducing setup time
D. Removing all registers

Q9. One-hot encoding of an N-state FSM uses:

A. log2(N) flip-flops
B. N flip-flops
C. N-1 flip-flops
D. 2N flip-flops

Q10. Pipeline registers primarily:

A. Reduce combinational delay per stage
B. Store only final outputs
C. Remove all hazards
D. Reduce setup time of FFs

Part B — Design & Analysis (10 × 7 = 70 pts)

For each problem, complete the Verilog template in the and verify using the provided self‑checking testbench. Name your top‑level modules exactly as specified.

Files provided (in the questions zip):

Templates: *.v (one per problem)
Testbenches: tb_*.v (one per problem)
Timescale: 1ns/1ps

Problems:

Problem 1 — Synchronizer + Edge Detect (sync_edge)
Synchronize asynchronous btn_async into clk with a two‑FF synchronizer; output btn_sync level and one‑cycle btn_pulse on rising edges. Active‑low rst_n.

Problem 2 — Dual‑Edge Capture (ddr_reg)
Capture D on posedge into Q_pos and on negedge into Q_neg. Active‑low rst_n.

Problem 3 — Mealy Sequence Detector “11010” (seq_11010_mealy)
Detect the overlapping pattern and assert Z on the final bit. Use a minimal FSM.

Problem 4 — Mod‑6 Up/Down Counter with Enable (mod6_counter)
3‑bit counter over 0..5. En gates counting; Dir=1 up, 0 down. Synchronous reset to 0.

Problem 5 — 4×4 Serial Multiplier Controller (mul4_ctrl)
Shift‑add controller with signals LdA,LdB,ClrP,Add,Shift,Done. Start with start=1. Iterate 4 times.

Problem 6 — 2‑Stage Pipeline (A+B)*C with Valid/Ready (pipe_add_mul)
Implement a two‑stage pipeline (add then multiply) with back‑pressure (in_valid/in_ready, out_valid/out_ready).

Problem 7 — CDC Bridge 1 MHz → 100 MHz (cdc_bridge)
Use a req/ack handshake and 2FF synchronizers both directions to transfer an 8‑bit word reliably.

Problem 8 — Moore FSM with Registered Output (moore_safe)
Provide both combinational output Zc and registered Zr (hazard‑free).

Problem 9 — Sequential 4‑bit ALU (seq_alu4)
Opcode: 00=ADD, 01=AND, 10=XOR, 11=SHL. Registered outputs Y and Cout with synchronous reset.

Problem 10 — Traffic Lights with Pedestrian Preempt (traffic_ped)
Main: G×3, Y×1; Side: G×2, Y×1. Insert WALK×4 at a safe point when ped_req=1; resume correctly.

Deliverables:

PDF with answers to Section A and brief design notes for Section B.
Verilog sources for all 10 designs.
Simulation logs/screenshots demonstrating passing testbenches.

Take-Home Midterm Exam: Sequential Circuits and Verilog

Tue, 28 Oct 2025 00:00:00 +0000

Scope: Sequential logic, finite state machines, registers, counters, with Verilog modeling
Duration: 48 hours
Instructions

Attempt all questions. Show reasoning, derivations, and clearly state assumptions.
Provide commented, synthesizable Verilog and a self‑checking testbench where requested.
Include brief timing/area reasoning (big‑O style or gate/count estimates).
No collaboration. Cite any external references you consulted.
Tutorial of Online tools for Verilog simulation can be found .

Part A — Multiple Choice (10 × 3 pts = 30 pts)

Select the best answer.

Part A — Multiple Choice (Keys)

Part A (MP) — Multiple Choice (Keys)

Part B — Design & Analysis (10 × 7 = 70 pts)

Download solutions .

Files provided (in the questions zip):

Templates: *.v (one per problem)
Testbenches: tb_*.v (one per problem)
Timescale: 1ns/1ps